356 search results - page 4 / 72 » Parallelizing time with polynomial circuits |
ACSD
2003
IEEE
14 years 10 days ago
2003
IEEE
Signal Transition Graphs (STGs) are one of the most popular models for the specification of asynchronous circuits. A STG can be implemented if it admits a so-called consistent an...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
CORR
2011
Springer
13 years 2 months ago
2011
Springer
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...