149 search results - page 15 / 30 » Parametric Fault Simulation and Test Vector Generation |
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
There has been considerable research on quantum dots cellular automata as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is a majorit...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We examine frequency-domain issues in the design and selection of on-chip test generators for built-in self-test (BIST) of highperformance digital filters. Test-generator/circuit...
ICRA
2006
IEEE
14 years 1 months ago
2006
IEEE
- In this article, a set membership (SM) identification technique is tailored to detect faults in microelectromechanical systems. The SM-identifier estimates an orthotope which con...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...