149 search results - page 17 / 30 » Parametric Fault Simulation and Test Vector Generation |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
ASPDAC
2004
ACM
14 years 25 days ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
EVOW
2001
Springer
13 years 12 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
DFT
2006
IEEE
13 years 9 months ago
2006
IEEE
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...