149 search results - page 4 / 30 » Parametric Fault Simulation and Test Vector Generation |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
ITC
2003
IEEE
14 years 19 days ago
2003
IEEE
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in s...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
DFT
2003
IEEE
14 years 19 days ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...