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» Parametric Fault Simulation and Test Vector Generation
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DATE
2007
IEEE
84views Hardware» more  DATE 2007»
14 years 1 months ago
On test generation by input cube avoidance
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
14 years 9 days ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
ICCAD
2000
IEEE
171views Hardware» more  ICCAD 2000»
13 years 11 months ago
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...
Michael Pronath, Volker Gloeckel, Helmut E. Graeb
DFT
2002
IEEE
108views VLSI» more  DFT 2002»
14 years 9 days ago
A Test-Vector Generation Methodology for Crosstalk Noise Faults
Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 5 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...