7 search results - page 1 / 2 » Parametric Yield Modeling and Simulations of FPGA Circuits C... |
TRETS
2008
13 years 10 months ago
2008
FPGA
2007
ACM
14 years 5 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
ICCAD
2005
IEEE
14 years 7 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ISQED
2005
IEEE
14 years 4 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...