96 search results - page 16 / 20 » Partially Reconfigurable Vector Processor for Embedded Appli... |
DAC
2006
ACM
14 years 1 months ago
2006
ACM
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...