618 search results - page 25 / 124 » Performance and energy optimization of concurrent pipelined ... |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
— In the past, dynamic voltage and frequency scaling (DVFS) has been widely used for power and energy optimization in embedded system design. As thermal issues become increasingl...
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...