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» Performance of Hardware Compressed Main Memory
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DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 2 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Energy and performance driven circuit design for emerging phase-change memory
Abstract--Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast acce...
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
IEEEPACT
2003
IEEE
14 years 1 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 16 days ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 1 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...