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» Performance of Hardware Compressed Main Memory
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VTS
2011
IEEE
278views Hardware» more  VTS 2011»
12 years 11 months ago
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...
Rudrajit Datta, Nur A. Touba
ASPLOS
1998
ACM
14 years 9 days ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 2 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
DEBS
2010
ACM
13 years 12 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...