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» Performance of a Software MPEG Video Decoder
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DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 1 months ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney
ICMCS
2006
IEEE
136views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Motion Aligned Spatial Scalable Video Coding
A motion aligned spatial scalable video coding scheme (MA-SSC) is proposed in this paper. Different from the traditional spatial scalable coding schemes derived from MPEG-2, in th...
Debing Liu, Yuwen He, Shipeng Li, Debin Zhao, Wen ...
DDECS
2007
IEEE
102views Hardware» more  DDECS 2007»
14 years 2 months ago
IP Integration Overhead Analysis in System-on-Chip Video Encoder
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. ...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
14 years 1 months ago
Performance improvement of the H.264/AVC deblocking filter using SIMD instructions
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
Stephen Warrington, Hassan Shojania, Subramania Su...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Rate analysis for streaming applications with on-chip buffer constraints
While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates tha...
Alexander Maxiaguine, Simon Künzli, Samarjit ...