70 search results - page 9 / 14 » Performance-Driven Interconnect Global Routing |
120
Voted
ICCAD
2003
IEEE
16 years 9 days ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
108
Voted
NOCS
2010
IEEE
15 years 1 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
134
Voted
ISPASS
2009
IEEE
15 years 10 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
108
click to vote
DAC
2009
ACM
16 years 4 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
126
Voted
IWSOS
2009
Springer
15 years 10 months ago
2009
Springer
The Internet consists of a constantly evolving complex hierarchical architecture where routers are grouped into autonomous systems (ASes) that interconnect to provide global connec...