70 search results - page 9 / 14 » Performance-Driven Interconnect Global Routing |
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
ISPASS
2009
IEEE
14 years 1 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
DAC
2009
ACM
14 years 7 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
IWSOS
2009
Springer
14 years 1 months ago
2009
Springer
The Internet consists of a constantly evolving complex hierarchical architecture where routers are grouped into autonomous systems (ASes) that interconnect to provide global connec...