34 search results - page 7 / 7 » Performance-centering optimization for system-level analog d... |
145
Voted
DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
127
Voted
ISCAS
2005
IEEE
15 years 9 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
140
Voted
VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
141
Voted
VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...