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» Placement of 3D ICs with Thermal and Interlayer Via Consider...
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ASPDAC
2007
ACM
164views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Thermal-Aware 3D IC Placement Via Transformation
- 3D IC technologies can help to improve circuit performance and lower power consumption by reducing wirelength. Also, 3D IC technology can be used to realize heterogeneous system-...
Jason Cong, Guojie Luo, Jie Wei, Yan Zhang
DAC
2011
ACM
12 years 7 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
14 years 5 days ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 4 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...