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ISCAS
1999
IEEE
132views Hardware» more  ISCAS 1999»
14 years 1 months ago
Dynamic trellis diagrams for optimized DSP code generation
In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal ...
Stefan Fröhlich, Martin Gotschlich, Udo Krebe...
TCSV
2008
102views more  TCSV 2008»
13 years 8 months ago
The Technique of Prescaled Integer Transform: Concept, Design and Applications
Integer cosine transform (ICT) is adopted by H.264/AVC for its bit-exact implementation and significant complexity reduction compared to the discrete cosine transform (DCT) with an...
Cixun Zhang, Lu Yu, Jian Lou, Wai-kuen Cham, Jie D...
ASPLOS
2010
ACM
14 years 7 hour ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 3 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
CASES
2007
ACM
14 years 21 days ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...