178 search results - page 1 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
ICCD
1997
IEEE
14 years 2 months ago
1997
IEEE
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
ISLPED
2003
ACM
14 years 4 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ICCAD
1994
IEEE
14 years 3 months ago
1994
IEEE
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...
TVLSI
2010
13 years 5 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...