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DSD
2008
IEEE
108views Hardware» more  DSD 2008»
13 years 9 months ago
Reducing Leakage through Filter Cache
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
Roberto Giorgi, Paolo Bennati
EMSOFT
2004
Springer
14 years 22 days ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
14 years 28 days ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 28 days ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee