1238 search results - page 13 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
DAC
2000
ACM
13 years 11 months ago
2000
ACM
DAC
2010
ACM
13 years 11 months ago
2010
ACM
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
ISPA
2007
Springer
14 years 1 months ago
2007
Springer
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...