296 search results - page 3 / 60 » Power Estimation in Sequential Circuits |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
EVOW
2000
Springer
13 years 11 months ago
2000
Springer
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
DAC
1996
ACM
14 years 7 days ago
1996
ACM
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
ISLPED
2000
ACM
13 years 11 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...