430 search results - page 20 / 86 » Power Optimized Combinational Logic Design |
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
DAC
2010
ACM
13 years 5 months ago
2010
ACM
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...