173 search results - page 1 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
GLVLSI
1998
IEEE
14 years 3 months ago
1998
IEEE
ISLPED
2000
ACM
14 years 3 months ago
2000
ACM
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
FPL
2010
Springer
13 years 8 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
DAC
2005
ACM
14 years 24 days ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...