21 search results - page 3 / 5 » Power-driven Design of Router Microarchitectures in On-chip ... |
MICRO
2003
IEEE
14 years 27 days ago
2003
IEEE
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
JNCA
2007
13 years 7 months ago
2007
As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router’s netwo...