85 search results - page 16 / 17 » Practical placement and routing techniques for analog circui... |
VLSID
2002
IEEE
13 years 12 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ISCAS
2005
IEEE
14 years 19 days ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...