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DAC
2005
ACM
14 years 9 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 3 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...
ASPDAC
2007
ACM
110views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Fast Placement Optimization of Power Supply Pads
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...
Yu Zhong, Martin D. F. Wong
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 5 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
DAC
2011
ACM
12 years 8 months ago
TPM-SIM: a framework for performance evaluation of trusted platform modules
This paper presents a simulation toolset for estimating the impact of Trusted Platform Modules (TPMs) on the performance of applications that use TPM services, especially in multi...
Jared Schmitz, Jason Loew, Jesse Elwell, Dmitry Po...