In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...