41 search results - page 4 / 9 » Process variation aware clock tree routing |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
ISQED
2002
IEEE
14 years 10 days ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...