63 search results - page 4 / 13 » Process variation robust clock tree routing |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
ISQED
2002
IEEE
14 years 14 days ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....