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» Race-condition-aware clock skew scheduling
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ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
14 years 4 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
DAC
2008
ACM
13 years 9 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
14 years 2 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...
DAC
1999
ACM
14 years 8 months ago
Maximizing Performance by Retiming and Clock Skew Scheduling
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Fast multi-domain clock skew scheduling for peak current reduction
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh