174 search results - page 5 / 35 » Reclocking for high-level synthesis |
TCAD
2011
13 years 2 months ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
ICES
2003
Springer
14 years 23 days ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...