30 search results - page 1 / 6 » Reduced Delay BCD Adder |
ASAP
2007
IEEE
14 years 2 months ago
2007
IEEE
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
ASIAMS
2008
IEEE
14 years 2 months ago
2008
IEEE
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...
ISMVL
1999
IEEE
13 years 12 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...