30 search results - page 3 / 6 » Reduced Delay BCD Adder |
CSREAESA
2004
13 years 9 months ago
2004
Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder d...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Decimal multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper pres...
GLVLSI
2003
IEEE
14 years 28 days ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
VLSI
2010
Springer
13 years 6 months ago
2010
Springer
—In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a larg...