24 search results - page 1 / 5 » Reduced Precision Checking for a Floating Point Adder |
DFT
2009
IEEE
14 years 26 days ago
2009
IEEE
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
ARITH
1999
IEEE
14 years 1 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract--The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined...
ARITH
2007
IEEE
14 years 4 months ago
2007
IEEE
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
ARITH
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...