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HPCA
2003
IEEE
16 years 3 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
123
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ICCD
2006
IEEE
109views Hardware» more  ICCD 2006»
16 years 10 days ago
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
Kuo-Su Hsiao, Chung-Ho Chen
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 8 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
127
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GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 8 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 7 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...