135 search results - page 10 / 27 » Reducing Power Dissipation in SRAM during Test |
SBCCI
2004
ACM
14 years 1 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
MTDT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
ITC
2003
IEEE
14 years 27 days ago
2003
IEEE
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
ICCD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...