135 search results - page 7 / 27 » Reducing Power Dissipation in SRAM during Test |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
TVLSI
1998
13 years 7 months ago
1998
Abstract— The growing popularity of look-up table (LUT)based field programmable gate arrays (FPGA’s) has renewed the interest in functional or Roth–Karp decomposition techni...