253 search results - page 1 / 51 » Reducing SoC Simulation and Development Time |
COMPUTER
2002
13 years 10 months ago
2002
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
IESS
2007
Springer
14 years 5 months ago
2007
Springer
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
DFT
2006
IEEE
14 years 4 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...