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» Reducing dTLB Energy Through Dynamic Resizing
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ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
14 years 4 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
13 years 11 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili
HPCA
2002
IEEE
14 years 8 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
ICASSP
2011
IEEE
12 years 11 months ago
Seam merging for image resizing with structure preservation
In image resizing process, preserving structure on an image is important to produce plausible results. We proposed seam merging, a seam-carving-based image resizing method, and a ...
Kazu Mishiba, Masaaki Ikehara
ISCAS
2002
IEEE
154views Hardware» more  ISCAS 2002»
14 years 16 days ago
Architectural approaches to reduce leakage energy in caches
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...
S. H. Tadas, C. Chakrabarti