43 search results - page 5 / 9 » Reducing the Energy of Speculative Instruction Schedulers |
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...
ISLPED
2003
ACM
14 years 20 days ago
2003
ACM
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
TCAD
2002
13 years 7 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...