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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 11 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
14 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
14 years 1 months ago
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
TASE
2008
IEEE
13 years 6 months ago
Steady-State Throughput and Scheduling Analysis of Multicluster Tools: A Decomposition Approach
Abstract--Cluster tools are widely used as semiconductor manufacturing equipment. While throughput analysis and scheduling of single-cluster tools have been well-studied, research ...
Jingang Yi, Shengwei Ding, Dezhen Song, Mike Tao Z...
TC
2002
13 years 7 months ago
On Augmenting Trace Cache for High-Bandwidth Value Prediction
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
Sang Jeong Lee, Pen-Chung Yew