73 search results - page 6 / 15 » Reduction of interpolants for logic synthesis |
IOLTS
2003
IEEE
14 years 27 days ago
2003
IEEE
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
PG
2007
IEEE
14 years 1 months ago
2007
IEEE
Interactive animation systems often use a level-of-detail (LOD) control to reduce the computational cost by eliminating unperceivable details of the scene. Most methods employ a m...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities...