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» Reliability challenges for 45nm and beyond
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ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
14 years 7 months ago
Design and CAD challenges in 45nm CMOS and beyond
With semiconductor industry's aggressive march towards 45nm
David J. Frank, Ruchir Puri, Dorel Toma
ASPLOS
2010
ACM
14 years 5 months ago
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
Engin Ipek, Jeremy Condit, Edmund B. Nightingale, ...
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 5 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
DAC
2010
ACM
14 years 2 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich