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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 3 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 6 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 6 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
MR
2007
107views Robotics» more  MR 2007»
13 years 8 months ago
Cohesive zone modeling for structural integrity analysis of IC interconnects
Due to the miniaturization of integrated circuits, their thermo-mechanical reliability tends to become a truly critical design criterion.
B. A. E. van Hal, R. H. J. Peerlings, M. G. D. Gee...
DAC
2009
ACM
14 years 3 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm