74 search results - page 13 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
GLVLSI
2010
IEEE
14 years 13 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...