768 search results - page 18 / 154 » Robustness of Sequential Circuits |
ICCAD
1996
IEEE
14 years 1 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
IFIP
1992
Springer
14 years 1 months ago
1992
Springer
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
DAC
1998
ACM
14 years 10 months ago
1998
ACM