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ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
14 years 2 months ago
Timing yield estimation using statistical static timing analysis
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
Min Pan, Chris C. N. Chu, Hai Zhou
DAC
1996
ACM
14 years 29 days ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng
DAC
1994
ACM
14 years 27 days ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
ICCD
1993
IEEE
124views Hardware» more  ICCD 1993»
14 years 28 days ago
Synthesis of Controllers from Interval Temporal Logic Specification
for a state machine which is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further ...
Masahiro Fujita, Shinji Kono
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
14 years 21 days ago
Variation resilient adaptive controller for subthreshold circuits
Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for powerlimited applications. For this design technique to gain widespread adoption...
Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolin...