29 search results - page 4 / 6 » SPIN-TEST: automatic test pattern generation for speed-indep... |
ATS
2003
IEEE
14 years 22 days ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
ATS
2009
IEEE
14 years 2 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...