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» SRAM Cell Current in Low Leakage Design
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ISCAS
2003
IEEE
124views Hardware» more  ISCAS 2003»
14 years 29 days ago
An active leakage-injection scheme applied to low-voltage SRAMs
ABSTRACT: An active leakage-injection scheme (ALIS) for lowvoltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a commond...
Jader A. De Lima
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
13 years 9 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
SOCC
2008
IEEE
151views Education» more  SOCC 2008»
14 years 2 months ago
Failure analysis for ultra low power nano-CMOS SRAM under process variations
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
DAC
2006
ACM
14 years 8 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
ISQED
2009
IEEE
106views Hardware» more  ISQED 2009»
14 years 2 months ago
Design and application of multimodal power gating structures
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
Ehsan Pakbaznia, Massoud Pedram