61 search results - page 9 / 13 » Scan chain clustering for test power reduction |
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
DELTA
2004
IEEE
13 years 11 months ago
2004
IEEE
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...