4 search results - page 1 / 1 » Scan-Chain Reordering for Minimizing Scan-Shift Power Based ... |
VTS
2008
IEEE
14 years 5 months ago
2008
IEEE
ITC
2003
IEEE
14 years 4 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
DFT
2005
IEEE
14 years 25 days ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...