133 search results - page 9 / 27 » Seamless integration of layout and simulation |
ENTCS
2007
13 years 7 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
AINA
2005
IEEE
13 years 9 months ago
2005
IEEE
—In this paper, a traffic aggregation based SIP over MPLS network architecture is proposed to integrate SIP protocol with traffic engineering (TE) enabled MPLS network seamlessly...
TCAD
1998
13 years 7 months ago
1998
— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...